Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a technology for protecting internal elements and internal circuits from electrostatic discharge (ESD).
Among internal circuits of integrated circuits (IC), semiconductor memory devices, and semiconductor devices, circuits configured with metal oxide semiconductor (MOS) components have high gate input impedance. Hence, gate oxide layers of MOS devices may be easily damaged by ESD. However, in fabricating high-performance and highly-integrated semiconductor devices, the thickness of gate oxide layers of transistors included in internal circuits is being decreased. Therefore, semiconductor devices are often provided with ESD protection circuits for protecting internal circuits from ESD.
Integrated circuits/semiconductor devices may be exposed to ESD during fabrication processes or in single-product states. This state is a non-operation state where no power is supplied because the integrated circuits/semiconductor devices are not yet mounted on electronic systems for normal operations.
Standard models for simulating ESD phenomenon are used to evaluate the tolerance and performance of ESD protection circuits and analyze the effect of ESD on the internal circuits. Generally, three ESD modeling methods are commonly used. The first ESD modeling method is a Human Body Model (HBM) which simulates the electrostatic charges charged in a human body that are discharged to a semiconductor device. The second ESD modeling method is a Machine Model (MM) which simulates the electrostatic charges charged in conductive machines that are discharged to a semiconductor device during semiconductor fabrication processing. The third ESD modeling method is a Charged Device Model (CDM) which simulates the electrostatic charges charged inside of a semiconductor device that are discharged to an external ground or conductor during fabrication processing, e.g., a packaging process. Electrostatic charges, i.e., positive charges or negative charges, charged in semiconductor devices are discharged by, for example, physical contact. Therefore, a flow direction of charges is determined by the polarity of charged charges.
An ESD protection circuit is configured with grounded-gate metal oxide semiconductor field effect transistor (ggMOSFET), gate-coupled MOSFET (gcMOSFET), bipolar junction transistor (BiT), diode, or other MOS components. When ESD occurs, the ggMOSFET, for example, clamps a voltage due to a parasitic BJT formed therein, and an over current flows through the ggMOSFET. During a normal operation in which no ESD occurs, the ESD protection circuit of the semiconductor device does not operate as a parasitic capacitance component, but may exhibit other properties such as a leakage current.
FIG. 1 illustrates a configuration of a conventional integrated circuit.
Referring to FIG. 1, the integrated circuit includes an input/output pad DQ, ESD protection units 10A and 10B, a pull-up drive transistor MP1, a first driving control unit 11UP, a dummy pull-up drive transistor MP2, a pull-down drive transistor MN1, a second driving control unit 11DN, and a dummy pull-down drive transistor MN2. Specifically, the input/output pad DQ is used for signal exchange with an external circuit. The ESD protection units 10A and 10B are connected to the input/output pad DQ to form an ESD path between a power supply voltage (VDD) line 13A and a ground voltage (VSS) line 13B. The pull-up drive transistor MP1 is connected between the VDD line 13A and the input/output pad DQ. The first driving control unit 11UP is connected to a gate of the pull-up drive transistor MP1 and configured to control the pull-up drive transistor MN. The dummy pull-up drive transistor MP2 is connected between the VDD line 13A and input/output pad DQ and has a gate connected to the VDD line 13A. The pull-down drive transistor MN1 is connected between the VSS line 13B and the input/output pad DQ. The second driving control unit 11DN is connected to a gate of the pull-down drive transistor MN1 and configured to control the pull-down drive transistor MN1. The dummy pull-down drive transistor MN2 is connected between the VSS line 13B and the input/output pad DQ and has a gate connected to the VSS line 13B.
The integrated circuit further includes a voltage clamping unit 12 connected between the VDD line 13A and the VSS line 13B. When a transient voltage or a transient current exceeds a certain level, the voltage clamping unit 12 forms an ESD path between the VDD line 13A and the VSS line 13B.
The ESD protection units 10A and 10B are configured with ggMOSFET, gcMOSFET, BJT, diode, and other MOS components. When ESD occurs, the ESD protection units 10A and 10B form a current path between the VDD line 13A and the VSS line 13B, thereby protecting the internal elements and internal circuits from over currents.
The internal circuit 14 controls the operations of the first driving control unit 11UP and the second driving control unit 11DN. The first driving control unit 11UP and the second driving control unit 11DN are also called a pre-driving unit.
The dummy pull-up drive transistor MP2 and the dummy pull-down drive transistor MN2 upon occurrence of ESD operate in the same manner as the pull-up drive transistor MP1 and the pull-down drive transistor MN1, that is, as a main output driving unit, due to the configuration of the integrated circuit. However, the dummy pull-up drive transistor MP2 and the dummy pull-down drive transistor MN2 do not drive the input/output pad DQ normally. The dummy drive transistors MP2 and MN2 are also referred to as “option fingers,” and the drive transistors MP1 and MN1 are also referred to as “driver fingers.”
The configuration and operation of the integrated circuit illustrated in FIG. 1 will be described below in detail.
In a normal operation mode, when power is supplied, a power supply voltage VDD is applied to a gate of the dummy pull-up drive transistor MP2, which is implemented with a PMOS transistor. In this case, since the dummy pull-up drive transistor MP2 maintains an off state, it does not affect signals transferred on the input/output pad DQ. Specifically, when the first driving control unit 11UP outputs a signal of a VSS level, the pull-up drive transistor MP1 is turned on to pull up the input/output pad DQ to the power supply voltage VDD. However, the dummy pull-up drive transistor MP2 maintains an off state in the normal operation mode.
Meanwhile, since no power is supplied to the VDD line 13A in a non-operation mode, an output terminal N1 of the first driving control unit 11UP and an output terminal N2 of the second driving control unit 11DN are set to a floating state. Thus, the gates of the pull-up drive transistor MP1 and the pull-down drive transistor MN1 are set to a floating state.
When ESD occurs at the input/output pad DQ, a voltage generated by static electricity is applied to the dummy drive transistors MP2 and MN2 and the drive transistors MP1 and MN1 until a current path is formed between VDD line 13A and VSS line 13B through the ESD protection units 10A and 10B. Due to the large voltage accompanying ESD, the dummy drive transistors MP2 and MN2 and the drive transistors MP1 and MN1 causes an over current to flow through the transistor due to the parasitic BJTs formed therein. However, while the gates of the drive transistors MP1 and MN1 are in a floating state, the gates of the dummy drive transistors MP2 and MN2 are connected to the VDD line 13A and the VSS line 13B, respectively. Therefore, trigger voltages at which the drive transistors MP1 and MN1 are turned on are lower than those of the drive transistors MP2 and MN2. In other words, since the drive transistors MP1 and MN1 are first turned on at ESD voltages lower than ESD voltages applied to the dummy drive transistors MP2 and MN2 to turn them on. Therefore, excessive stress is generated in the drive transistors MP1 and MN1 at an early stage, causing the damage of the drive transistors MP1 and MN1.